CPLD的分频语言

分频器在FPGA/CPLD设计中是不可缺少的一部分，这就包括分频系数是奇数和偶数的（我们称为奇分频和偶分频），而对于偶分频来说还有不同的分频方法，下面将给出具体的方法：

1、占空比不为50%的偶分频

占空比：指在一个周期内高低电平持续的时间不等。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; --定义库文件
entity ofp is         --定义实体名为ofp
port(
     clk:in std_logic;
     clk_fp:out std_logic);
end entity;
architecture miao of ofp is
signal n:integer range 0 to 3;--4分频注意：要想得到别的偶数分频

                             --可以将3替换为 fp_num-1 (fp_num为分频系数)
begin
process(clk)
begin
if clk'event and clk='1' then    --时钟上升沿触发
   if n<3 then             --当计数器n<3时进行+1运算，当n=3时n返回0
      n<=n+1;clk_fp<='0';
   else
   n<=0;clk_fp<='1';
   end if;
end if;
end process;
end miao;

2、占空比为50%的偶分频

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;--定义库文件
entity ofp1 is --定义实体名为ofp1
port(
clk:in std_logic;
clk_fp:out std_logic);
end entity;
architecture miao of ofp1 is
signal n:integer range 0 to 1;--注意：同样是四分频，这里n只是0-1

-- 注意：要想得到别的偶数分频

--可以将1替换为 fp_num/2 -1 (fp_num为分频系数)

signal cp:std_logic; --定义一个中间变量，因为port内的输出信号不能放在- ---赋值号的右边
begin
process(clk)
begin
if clk'event and clk='1'then --思想：当计数器n计数到1的时候就将信号

                             --cp进行翻转
   if n<1 then
      n<=n+1;
   else
   n<=0;cp<=not cp;
   end if;
end if;
end process;
clk_fp<=cp;
end miao;

3、占空比不为50%的奇分频

下面这个程序是3分频的程序，要是大家想改为别的，就尝试一下吧，我就不明说了，要是真的不知道，可以留言

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity thirdfreq is
port(
   clkin : in STD_LOGIC;
   rst : in STD_LOGIC;
   thirdfreq : out STD_LOGIC;    -- three freq output, 50%
   threecountp : out STD_LOGIC_VECTOR(1 downto 0); --not 50%
   threecountn : out STD_LOGIC_VECTOR(1 downto 0) --not 50%
      );
end thirdfreq;
architecture thirdfreq of thirdfreq is
signal threecntp   : std_logic_vector(1 downto 0);
signal threecntn   : std_logic_vector(1 downto 0);
signal thirdfreq_p : std_logic;
signal thirdfreq_n : std_logic;
begin
thirdfreq <= thirdfreq_p and thirdfreq_n;
u0: process(clkin,rst)
begin
if rst = '0' then
   threecntp <= "00";
else
   if clkin'event and clkin = '1' then
    if threecntp = "10" then
     threecntp <= "00";
    else
     threecntp <= threecntp + '1';
    end if;
   end if;
end if;
end process u0;
threecountp <= threecntp;

u1: process(clkin,rst)
begin
if rst = '0' then
   threecntn <= "00";
else
   if clkin'event and clkin = '0' then
    if threecntn = "10" then
     threecntn <= "00";
    else
     threecntn <= threecntn + '1';
    end if;
   end if;
end if;
end process u1;
threecountn <= threecntn;

u2: process(clkin,rst)
begin
if rst = '0' then
   thirdfreq_p <= '0';
else
   if clkin'event and clkin = '1' then
    if threecntp < "01" then
     thirdfreq_p <= '0';
    else
     thirdfreq_p <= '1';
    end if;
   end if;
end if;
end process u2;

u3: process(clkin,rst)
begin
if rst = '0' then
   thirdfreq_n <= '0';
else
   if clkin'event and clkin = '0' then
    if threecntn < "01" then
     thirdfreq_n <= '0';
    else
     thirdfreq_n <= '1';
    end if;
   end if;
end if;
end process u3;
end thirdfreq;